FPGA logo

 

This documentation applies to both our FPGA Server lab and our FPGA-as-a-Service by Accelize lab.

Documentation: FPGA server

An FPGA (Field-Programmable Gate Array) is a special chip that can be configured at low level to act as any digital electronic circuit. It can be used as an accelerator specifically tailored to a given use case. To use an FPGA, two elements are required: a bitfile to configure the hardware part properly, and a software driver for the system to communicate with the FPGA.

An FPGA server is a standard dedicated server with an FPGA board connected to the CPU through both PCIe and USB. The USB connection is used for configuring the FPGA and for monitoring. The PCIe connection can be used to transfer data between the CPU and the FPGA. The board also has DDR4 memory directly connected to the FPGA (see detailed specifications of the board).

FPGA servers are part of an OVH lab in early stage and are continually improved. If you have feedback, questions or suggestions, do not hesitate to contact us on hardware.labs@ml.ovh.net.

There are different solutions to use the FPGA depending on your requirements:

Solution Ready-made accelerators Custom accelerator
  OpenCL Low-level (Verilog/VHDL)
No hardware experience required
Software-like dev. environment
Performance Optimal Depends on the application Optimal
Customizability Software only Total Total
Documentation Use ready-made accelerators Develop your own accelerator Contact us

 

Depending on the chosen method, we provide two preconfigured images that you can install on your dedicated server:

  • CentOS 7 FPGA Accelize
  • CentOS 7 FPGA Intel Opencl

Accelize logo
Use ready-made accelerators with our partner Accelize

Accelize provides accelerators for FPGAs that can be used immediately. They use the best components available from their IP partners to build efficient accelerators.

To use these accelerators on FPGA servers, just install the "CentOS 7 FPGA Accelize" image on (Manager > Button "Install" or "Reinstall" > "Install from an OVH template" > "CentOS 7 FPGA Accelize").

The accelerator is immediately available. For now the only accelerator is gzip compression and decompression. Use the "gzip_fpga" command instead of the "gzip" command to accelerate gzip compression or decompression.

Other accelerators are coming very soon. They will be available on the machine through updates. A reconfiguration of the FPGA will be necessary to use other accelerators. We will describe here the commands to run for the reconfiguration.

Support

If you have problems with an accelerator or if you need other accelerators, you can ask for support on hardware.labs@ml.ovh.net.

Intel FPGA logo
Develop your own accelerator directly on the FPGA

To develop your own application, you need to get familiar with tools from Intel FPGA (previously Altera).

Development

For now, we only provide tools for OpenCL development. But if you are interested in HDL development, do not hesitate to contact us.

The development requires:

Developing on the FPGA server is not necessary or advised. Compilation (synthesis) requires a lot of RAM and fast processors. Public cloud instances are very handy for FPGA development. We use them internally and we can help and provide pre-installed images if required.

Deployment

Install the "CentOS 7 FPGA Intel Opencl" image on your FPGA server (Manager > Button "Install" or "Reinstall" > "Install from an OVH template" > "CentOS 7 FPGA Intel Opencl")

This installs all tools required to use OpenCL applications. You just need to put the sources of your application on the machine, compile the software part (the hardware part has to be previously compiled with Intel FPGA tools), and run it.

An example application (Hello World) is available in the directory "/opt/altera/examples". To use it, go to the example directory, run make, go the the "bin" directory, and run the executable.

Advanced deployment tips

The image pre-loaded in the FPGA should work with any OpenCL kernel. But if you want to update it, you will have to convert the image provided after the synthesis (top.sof) into an image that can be loaded into the FPGA (rpd file). For that, use this command:

quartus_cpf -o options.txt -c -d EPCQL512 -m ASx4 top.sof top.pof

The options.txt file has to be created before running the command with this content:

bitstream_compression=on
memory_map_file=on
auto_create_rpd=on

To load the image into the FPGA, just run this command:

load_fpga path/to/image.rpd

Support

If you have problems with OpenCL development, the Intel FPGA website has documentation. If you have problems with the FPGA board, you can ask for support on hardware.labs@ml.ovh.net.